Dongwoon Anatech Licenses Codasip’s Bk3 RISC-V Processor for Motor Control ICs for Mobile Camera

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Brno, Czech Republic, and Seoul, Korea – March 23rd 2018 – Codasip, the leading supplier of RISC-V® embedded processor IP, announced today that Dongwoon Anatech, a technology leader in analog and power ICs for mobile phones, has selected Codasip’s Bk3 processor and Studio design tool for its next generation family of motor control IC products. Dongwoon Anatech, fabless analog semiconductor …

RISC-V Shows Growing Momentum and Ecosystem at Embedded World 2018

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Embedded World 2018, the international trade fair for embedded systems, took place between February 27th and March 1st in Nuremberg, Germany. This year, the event enjoyed a record number of participants and a strong presence of RISC-V. In 2016, a visitor to Embedded World saw a set of offerings almost identical to the previous decade – the same semiconductor vendors, software development tool companies, system level offerings. The dominant …

Trinamic Licenses Codasip’s Bk3 RISC-V Processor for Next Generation Motion Control Applications

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Brno, Czech Republic and Hamburg, Germany – February 28th 2018 – Codasip, the leading supplier of RISC-V® embedded processor IP, announced today that Trinamic, the global leader in embedded motor and motion control ICs and microsystems, has selected Codasip’s Bk3 processor for its next-generation family of products. Trinamic’s products serve multiple markets including laboratory and factory automation, semiconductor manufacturing, textiles, robotics, ATMs, and …

Rambus Selects Codasip Studio for SDK Development of RISC-V Processor

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Brno, Czech Republic – November 14th 2017 – Codasip, Ltd., the leader in RISC-V embedded processor IP cores, today announced that Rambus selected Codasip Studio for developing its next-generation RISC-V security products. Codasip Studio provides fully automated generation of the Software Design Kit (SDK) for RISC-V processors. Codasip Studio utilizes a high-level design flow based on a proprietary modeling language …

Codasip and Avery Partner to Improve Regression Test Methodology of RISC-V Processors

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Brno, Czech Republic – November 8th 2017 – Codasip, the leading supplier of RISC-V® embedded CPU cores, today announced its partnership with Avery Design Systems, the provider of cutting-edge verification intellectual property (VIP) solutions for SoC and IP companies. Codasip develops licensable RISC-V processors, the Berkelium (Bk) series, via a unique customization tool called Codasip Studio, allowing for fast configuration and optimization of the cores. Studio enables practically …

Codasip to present at Mentor Forums for Emulation in India

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Hyderabad, India | 10 October, 2017 Bangalore, India | 12 October, 2017 As the verification and validation requirements for modern systems become more and more complex, hardware emulation with its versatility becomes the methodology to go to. At Mentor Forums for Emulation 2017, this shift in emulation usage will be explained and discussed through a number of talks by highly …

BaySand, Codasip, Codeplay and UltraSoC accelerate IoT development with “silicon-to-intelligence” RISC-V platform

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MOUNTAIN VIEW, CA, 29th November 2016 BaySand, Codasip, Codeplay and UltraSoC today announced an integrated IoT development platform based on the RISC-V open processor instruction set architecture (ISA).  The platform offers an open-standards-based solution that allows designers of systems-on-a-chip (SoCs) for IoT applications to get from concept to silicon with a high level of software integration in record time and …

Codasip and CAST collaboration ships first products to customers

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AUSTIN, TEXAS — Design Automation Conference — June 6, 2016 — Codasip, a leading provider of Application Specific Instruction-set Processor (ASIP) IP and tools, and CAST, a semiconductor intellectual property (IP) provider, announced today that the first CAST products created using Codasip’s tools are now available to customers. Codasip™ Studio, a comprehensive ASIP development environment, is able to generate a …