Codix Processors and Subsystems


Your SoC design is unique, so why isn’t your embedded processor?

Codix Cores represent a new approach to embedded processor IP allowing tailoring to the exact needs of your embedded software – providing lower power, higher performance, smaller code size, and smaller area than other IP cores.

CODIX HELIUM

Ideal for applications that demand performance and low power. Rich instruction set, variable-length instructions and compact code.

CODIX COBALT

Excellent general purpose embedded processor for ASIC and FPGA design with unique instruction-set features .

CODIX BERKELIUM

Delivers RISC-V instruction-set compatibility with the option of ZScale or Rocket-like architectures.

CODIX TITANIUM

Powerful multi-slot VLIW processor with a Von-Neumann architecture. It is ideal for applications that require a powerful compact core.

Comparison Table



HELIUM

COBALT

BERKELIUM

TITANIUM

Main Features and Intended Use

High Performance

 

 

Low Power, IoT

 

 

Low Area

 

 

Well-known ISA

 

 

 

Image Processing

 

 

 

Linux/FreeRTOS Support

 

 

Baseline Technical Parameters

ISA

Proprietary

Proprietary

RISC-V

Proprietary

Instructions Length

Variable-length
16/24/32 bit

Fixed-length
32 bit

RV32IM (ZScale)
RV64IM (Rocket)

Fixed-length
4×32 bit

Pipeline Stages

3

5

3/5

5

Registers

16/32 × 32b

32 × 32b

32 × 32b/64b

32 × 32b

Bus Type

CLB/AHB/AXI

CLB/AHB/AXI

CLB/AHB/AXI

CLB/AHB/AXI

  • Each Codix Core can be expanded with optional JTAG Debugger, L1 Cache, L2 Cache, HW Divider/Multiplier, Floating Point Unit and Interrupts System

CODIX HELIUM


Codix Helium is ideal for applications that demand performance and low power. Thanks to its rich instruction set and variable-length instructions, Codix Helium delivers far higher performance than other processors in this class, as well as very compact code size.

As with all Codix Cores, every aspect of the Codix Helium can be modified or extended.

  • Variable-length16/24/32 bit instructions
  • 3-stage pipeline
  • 16/32 × 32b general purpose registers
  • Hardware hazard detection
  • Optional floating point
  • Optional instruction and data cache
  • Interrupt support
  • Sleep mode support
  • Optional JTAG support
  • < 0.02mm² in 40LP

CODIX HELIUM


Codix Helium is ideal for applications that demand performance and low power. Thanks to its rich instruction set and variable-length instructions, Codix Helium delivers far higher performance than other processors in this class, as well as very compact code size.

As with all Codix Cores, every aspect of the Codix Helium can be modified or extended.

  • Variable-length16/24/32 bit instructions
  • 3-stage pipeline
  • 16/32 × 32b general purpose registers
  • Hardware hazard detection
  • Optional floating point
  • Optional instruction and data cache
  • Interrupt support
  • Sleep mode support
  • Optional JTAG support
  • < 0.02mm² in 40LP

CODIX COBALT


Codix Cobalt is an excellent general purpose embedded processor for ASIC and FPGA design with unique instruction-set features that allow it to deliver great performance with lower power and smaller area. The processor’s optimized 5-stage pipeline allows it to work over a very wide frequency range.

Codix Cobalt comes with standard peripherals allowing development using FreeRTOS, Linux, Microsoft® .NET Micro Framework and other embedded development environments.

As with all Codix Cores, every aspect of the Codix Cobalt can be modified or extended.

  • Fixed-length instructions 32 bits
  • 5-stage pipeline
  • 32 × 32b general purpose registers
  • Compiler-based data hazard avoidance
  • Interrupt support
  • < 0.03mm² in 40nm
  • Optional floating point
  • Optional instruction and data cache
  • Optional Branch Prediction Unit
  • Optional JTAG support
  • Optional sleep mode support

CODIX COBALT


Codix Cobalt is an excellent general purpose embedded processor for ASIC and FPGA design with unique instruction-set features that allow it to deliver great performance with lower power and smaller area. The processor’s optimized 5-stage pipeline allows it to work over a very wide frequency range.

Codix Cobalt comes with standard peripherals allowing development using FreeRTOS, Linux, Microsoft® .NET Micro Framework and other embedded development environments.

As with all Codix Cores, every aspect of the Codix Cobal can be modified or extended.

  • Fixed-length instructions 32 bits
  • 5-stage pipeline
  • 32 × 32b general purpose registers
  • Compiler-based data hazard avoidance
  • Interrupt support
  • < 0.03mm² in 40nm
  • Optional floating point
  • Optional instruction and data cache
  • Optional Branch Prediction Unit
  • Optional JTAG support
  • Optional sleep mode support

CODIX BERKELIUM


Codix Berkelium delivers RISC-V instruction-set compatibility with the option of ZScale or Rocket-like architectures, allowing users to leverage the rich ecosystem of software and tools becoming available, in addition to those provided by Codasip.

Codix Berkelium comes with standard peripherals allowing development using OS’ ported to RISC-V including Linux and FreeRTOS.

As with all Codix Cores, every aspect of the Codix Berkelium can be modified or extended.

  • Support for RV32IM/RV64IM
  • 3-stage or 5-stage pipeline options
  • 32 or 64bit general purpose registers
  • Optional floating point extensions (“F”)
  • Optional atomic instructions (“A”)
  • Optional instruction pre-fetch
  • Optional instruction and data cache
  • Optional interrupt support
  • < 0.10mm² in 40LP (ZScale is significantly smaller)

CODIX BERKELIUM


Codix Berkelium delivers RISC-V instruction-set compatibility with the option of ZScale or Rocket-like architectures, allowing users to leverage the rich ecosystem of software and tools becoming available, in addition to those provided by Codasip.

Codix Berkelium comes with standard peripherals allowing development using OS’ ported to RISC-V including Linux and FreeRTOS.

As with all Codix Cores, every aspect of the Codix Berkelium can be modified or extended.

  • Support for RV32IM/RV64IM
  • 3-stage or 5-stage pipeline options
  • 32 or 64bit general purpose registers
  • Optional floating point extensions (“F”)
  • Optional atomic instructions (“A”)
  • Optional instruction pre-fetch
  • Optional instruction and data cache
  • Optional interrupt support
  • < 0.10mm² in 40LP (ZScale is significantly smaller)

CODIX TITANIUM


Codix Titanium is a powerful 4-slot VLIW processor with a Von-Neumann architecture. It is ideal for applications that require a powerful but compact core and exhibit a high degree of parallelism-image processing, computer vision, and software defined radio, for example.

The Codix Titanium SDK supports multi-issue and is latency aware for both instruction and data access, allowing for highly efficient instruction scheduling. Codasip’s profiling and debug tools also fully support VLIW designs.

As with all Codix Cores, every aspect of the Codix Titanium can be modified or extended. The default configuration utilizes 4 slots.

  • 4 execution units using 5-stage pipelines
  • Bundle contains 4 instructions of 32bits
  • 32 × 32b general purpose registers
  • 8 × 1b predicate registers
  • 32b status register
  • Data hazards handled by compiler
  • < 0.09mm² in 40LP
  • 2 separate Load/Store Units, ALU and MUL in each slot, 1 Branch Prediction Unit
  • Single port instruction and dual data port cache
  • Predicate is computed in 2 slots, but can be used in all of them
  • Structural and Control hazards handled by hardware

CODIX TITANIUM


Codix Titanium is a powerful 4-slot VLIW processor with a Von-Neumann architecture. It is ideal for applications that require a powerful but compact core and exhibit a high degree of parallelism-image processing, computer vision, and software defined radio, for example.

The Codix Titanium SDK supports multi-issue and is latency aware for both instruction and data access, allowing for highly efficient instruction scheduling. Codasip’s profiling and debug tools also fully support VLIW designs.

As with all Codix Cores, every aspect of the Codix Titanium can be modified or extended. The default configuration utilizes 4 slots.

  • 4 execution units using 5-stage pipelines
  • Bundle contains 4 instructions of 32bits
  • 32 × 32b general purpose registers
  • 8 × 1b predicate registers
  • 32b status register
  • Data hazards handled by compiler
  • < 0.09mm² in 40LP
  • 2 separate Load/Store Units, ALU and MUL in each slot, 1 Branch Prediction Unit
  • Single port instruction and dual data port cache
  • Predicate is computed in 2 slots, but can be used in all of them
  • Structural and Control hazards handled by hardware

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