Codix Processors and Subsystems


Your SoC design is unique, so why isn’t your embedded processor?

Codix Cores represent a new approach to embedded processor IP allowing tailoring to the exact needs of your embedded software – providing lower power, higher performance, smaller code size, and smaller area than other IP cores.

CODIX HELIUM

Ideal for applications that above all require low power. Rich instruction set, variable-length instructions, compact code.

CODIX BERKELIUM

Compatible with the RISC-V instruction set, highly customizable and offering support for additional architectures.

CODIX TITANIUM

Powerful multi-slot VLIW processor with Von Neumann architecture, for applications that need a powerful compact core.

Comparison Table



HELIUM

BERKELIUM

TITANIUM

Main Features and Intended Use

High Performance

 

Low Power, IoT

 

Low Area

 

Well-known ISA

 

 

Image Processing

 

 

FreeRTOS Support

 

 

Baseline Technical Parameters

ISA

Proprietary

RISC-V

Proprietary

Instructions Length

Variable-length
16/24/32 bit

RV32I/E MC
RV32/64IM/F

Fixed-length
4×32 bit

Pipeline Stages

3

1 / 3 / 5

5

Registers

16/32 × 32b

16/32 × 32b/64b

32 × 32b

Bus Type

CLB/AHB/AXI

CLB/AHB/AXI

CLB/AHB/AXI


Each Codix Core can be extended with optional JTAG Debugger, L1 Cache, L2 Cache, HW Divider/Multiplier, Floating Point Unit, and Interrupts System.

CODIX HELIUM


Codix Helium is ideal for applications that demand performance and low power. Thanks to its rich instruction set and variable-length instructions, Codix Helium delivers far higher performance than other processors in this class, as well as very compact code size.

As with all Codix Cores, every aspect of the Codix Helium can be modified or extended.

  • Variable-length 16/24/32 bit instructions
  • 3-stage pipeline
  • 16/32 × 32b general purpose registers
  • Hardware hazard detection
  • Optional floating point
  • Optional instruction and data cache
  • Interrupt and sleep mode support
  • Optional JTAG support
  • 9–18k gates in 55 LP
  • Frequency 200–250 MHz in 55 LP

CODIX HELIUM


Codix Helium is ideal for applications that demand performance and low power. Thanks to its rich instruction set and variable-length instructions, Codix Helium delivers far higher performance than other processors in this class, as well as very compact code size.

As with all Codix Cores, every aspect of the Codix Helium can be modified or extended.

  • Variable-length 16/24/32 bit instructions
  • 3-stage pipeline
  • 16/32 × 32b general purpose registers
  • Hardware hazard detection
  • Optional floating point
  • Optional instruction and data cache
  • Interrupt support
  • Sleep mode support
  • Optional JTAG support
  • 9–18k gates in 55 LP
  • Frequency 200–250 MHz in 55 LP

CODIX BERKELIUM


Codix Berkelium delivers RISC-V instruction-set compatibility with the option of various architectures, allowing users to take full advantage of the rich ecosystem of software and tools that are becoming available, in addition to those provided by Codasip.

As with all Codix Cores, every aspect of the Codix Berkelium can be modified or extended.

  • Support for RV32[I|E]MC and RV64IMF
  • 1, 3 or 5-stage pipeline options
  • 32 or 64bit general purpose registers
  • Optional floating point extension (“F”)
  • Sleep mode support
  • Optional instruction and data cache
  • Interrupt support
  • JTAG debug support
  • 9–25k gates in 55 LP
  • Frequency 350–550 MHz in 55 LP

CODIX BERKELIUM


Codix Berkelium delivers RISC-V instruction-set compatibility with the option of various architectures, allowing users to take full advantage of the rich ecosystem of software and tools that are becoming available, in addition to those provided by Codasip.

As with all Codix Cores, every aspect of the Codix Berkelium can be modified or extended.

  • Support for RV32I/E MC and RV64IMF
  • 1, 3 or 5-stage pipeline options
  • 32 or 64bit general purpose registers
  • Optional floating point extensions (“F”)
  • Sleep mode support
  • Optional instruction and data cache
  • Interrupt support
  • JTAG debug support
  • 9k–25k gates in 55 LP
  • Frequency 350–550 MHz in 55 LP

CODIX TITANIUM


Codix Titanium is a powerful 4-slot VLIW processor with Von Neumann architecture. It is ideal for applications that require a powerful but compact core, with high degree of parallelism image processing, computer vision, and software defined radio, for example.

The Codix Titanium SDK supports multi issue, and is latency-aware for both instruction and data access, allowing for highly efficient instruction scheduling. Codasip’s profiling and debugging tools also fully support VLIW designs.

As with all Codix Cores, every aspect of the Codix Titanium can be modified or extended. Default configuration uses 4 slots.

  • 4 execution units using 5-stage pipelines
  • Bundle contains 4 instructions of 32bits
  • 32 × 32b general purpose registers
  • 8 × 1b predicate registers
  • 32b status register
  • Data hazards handled by compiler
  • 61k gates in 55 LP
  • 2 separate Load/Store Units, ALU and MUL in each slot, 1 Branch Prediction Unit
  • Single port instruction and dual data port cache
  • Predicate computed in 2 slots, optionally in all
  • Structural and Control hazards handled by hardware
  • Frequency 446 MHz in 55 LP

CODIX TITANIUM


Codix Titanium is a powerful 4-slot VLIW processor with Von Neumann architecture. It is ideal for applications that require a powerful but compact core, with high degree of parallelism image processing, computer vision, and software defined radio, for example.

The Codix Titanium SDK supports multi issue, and is latency-aware for both instruction and data access, allowing for highly efficient instruction scheduling. Codasip’s profiling and debugging tools also fully support VLIW designs.

As with all Codix Cores, every aspect of the Codix Titanium can be modified or extended. Default configuration uses 4 slots.

  • 4 execution units using 5-stage pipelines
  • Bundle contains 4 instructions of 32bits
  • 32 × 32b general purpose registers
  • 8 × 1b predicate registers
  • 32b status register
  • Data hazards handled by compiler
  • 61k gates in 55 LP
  • 2 separate Load/Store Units, ALU and MUL in each slot, 1 Branch Prediction Unit
  • Single port instruction and dual data port cache
  • Predicate is computed in 2 slots, but can be used in all of them
  • Structural and Control hazards handled by hardware
  • Frequency 446 MHz in 55 LP

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  Helium  Berkelium  Titanium