Codasip Studio and Codasip CodeSpace 6.5 available

Product Releases

We are proud to announce that the Codasip Studio and Codasip CodeSpace in version 6.5 are available for download. This release includes many improvements and new features including: LLVM 3.9.1 with a new smart code size reduction feature Enhanced debugging including a new scripting support Enhanced profiling including CodAL Expression Coverage More flexibility in a definition of reset modes in RTL …

RISC-V Enters Mainstream at Embedded World 2017

Press Releases

Berkeley, California – Over the last year the RISC-V architecture has evolved from an academic research interest to a mainstream embedded processor technology with a rich ecosystem and a fast-growing number of real-world implementations. As a sign of this progress, a number of companies will be demonstrating commercial implementations of RISC-V products next week at Embedded World 2017, the leading international …

Codasip and TVS Deliver Advanced RISC-V Verification Solutions

Press Releases

Brno, Czech Republic – March 10th 2017 – Codasip, a leading RISC-V processor IP provider, and T&VS (Test and Verification Solutions), a leading verification services provider for semiconductor IP, hardware and software, today announced a broad collaboration to accelerate the verification of products based on the Codix-Bk series of RISC-V compliant processor cores. The partnership ensures companies can be confident …

Visit Codasip @Verification Futures 2017


Visit Codasip at Verification Futures 2017 We are happy to announce that Codasip will be part of the Verification Futures 2017 conference and exhibition, which takes place in Reading on 6th April 2017. Our speaker Andrew Betts will present the challenges and strategies for RISC-V functional verification. Verification Futures 2017

Visit Codasip @REUSE2016


Visit Codasip at REUSE2016. We are happy to be part of REUSE2016 event Dec 1st 2016 with Codasip RISC-V processor IP and Processor development tools.

BaySand, Codasip, Codeplay and UltraSoC accelerate IoT development with “silicon-to-intelligence” RISC-V platform

Press Releases

MOUNTAIN VIEW, CA, 29th November 2016 BaySand, Codasip, Codeplay and UltraSoC today announced an integrated IoT development platform based on the RISC-V open processor instruction set architecture (ISA).  The platform offers an open-standards-based solution that allows designers of systems-on-a-chip (SoCs) for IoT applications to get from concept to silicon with a high level of software integration in record time and …

Codasip and UltraSoC deliver advanced RISC-V SoC analysis and debug

Press Releases

San Jose, CA – Nov 22nd – Codasip, the leading RISC-V processor IP provider, and UltraSoC, the leading provider of semiconductor IP for on-chip analytics, performance optimization and hardware-based security and debug, announced a broad collaboration to integrate the Codix-Bk series of RISC-V compliant processor cores seamlessly with the UltraSoC environment. As RISC-V based SoCs enter the mainstream, the need …

Visit Codasip @SemIsrael


We are excited to be part of the SemIsrael event Nov 15th 2016. If you are planning on being there drop by and find out more about Codasip IP, RISC-V and Processor development tools.

Codasip and BaySand Partnership Makes RISC-V Based ASICs an Ideal Choice for IoT Designs

Press Releases

San Jose, CA – Nov 9th 2016 – Codasip, a leading-edge processor IP provider, and BaySand, the leader in application configurable ASICs, announced that they are collaborating to make the Codix-Bk series of RISC-V compliant processor cores available on BaySand’s new UltraShuttle service in 65nm and 40nm. RISC-V is becoming a pivotal processor standard for leading-edge IoT device designs, and …