Codasip Studio and Codasip CodeSpace 7.0 available

News & Docs, Press Releases

Codasip CodeSpace and Codasip Studio are available for download in the latest version 7.0. The tools contain new features including: Update to Codasip MINGW 2, which includes MSYS2 and gcc 6.4.0 New interface methods in CodAL Integration of LLVM 5.0.0 Experimental support for AMBA busses For a full list of features please login to the support area and check the …

Codasip Announces Bk5-64, a New 64-bit RISC-V Processor

News & Docs, Press Releases

Brno, Czech Republic – November 28th, 2017 – Codasip, the leading supplier of RISC-V® embedded processor IP, today announced that it has expanded its Berkelium processor portfolio to include the Bk5-64, its first implementation of the 64-bit RISC-V ISA. Codasip now offers customers the broadest selection of RISC-V processors in the market, spanning from the ultra-low-power zero-stage Bk1 to the high-data-bandwidth, …

Rambus Selects Codasip Studio for SDK Development of RISC-V Processor

Press Releases

Brno, Czech Republic – November 14th 2017 – Codasip, Ltd., the leader in RISC-V embedded processor IP cores, today announced that Rambus selected Codasip Studio for developing its next-generation RISC-V security products. Codasip Studio provides fully automated generation of the Software Design Kit (SDK) for RISC-V processors. Codasip Studio utilizes a high-level design flow based on a proprietary modeling language …

Codasip and Avery Partner to Improve Regression Test Methodology of RISC-V Processors

Press Releases

Brno, Czech Republic – November 8th 2017 – Codasip, the leading supplier of RISC-V® embedded CPU cores, today announced its partnership with Avery Design Systems, the provider of cutting-edge verification intellectual property (VIP) solutions for SoC and IP companies. Codasip develops licensable RISC-V processors, the Berkelium (Bk) series, via a unique customization tool called Codasip Studio, allowing for fast configuration and optimization of the cores. Studio enables practically …

Codasip Hires IP Industry Veteran Chris Jones as Vice President of Marketing

News & Docs, Press Releases

Brno, Czech Republic – October 16th 2017 – Codasip, the leading supplier of RISC-V® embedded CPU cores, today announced that Chris Jones has joined as Vice President of Marketing, reporting to CEO Karel Masařík. “We are very pleased to add Chris to the Codasip executive team,” declared Karel Masařík, CEO and founder of Codasip. “As we execute our strategy to be the leading supplier of RISC-V based …

Codasip Announces Latest RISC-V Processor

News & Docs, Press Releases

The Newest Codasip RISC-V Processor is Ideal for IoT Designs Brno, Czech Republic – August 21st 2017 – Codasip, the leading supplier of RISC-V® embedded CPU cores, today announced the newest addition to their Berkelium (Bk) family of RISC-V processors. The Codasip Bk-1 processor is an FSM processor targeted at the Internet of Things (IoT) by offering ultra-low power, the …

RISC-V Enters Mainstream at Embedded World 2017

Press Releases

Berkeley, California – Over the last year the RISC-V architecture has evolved from an academic research interest to a mainstream embedded processor technology with a rich ecosystem and a fast-growing number of real-world implementations. As a sign of this progress, a number of companies will be demonstrating commercial implementations of RISC-V products next week at Embedded World 2017, the leading international …

Codasip and TVS Deliver Advanced RISC-V Verification Solutions

Press Releases

Brno, Czech Republic – March 10th 2017 – Codasip, a leading RISC-V processor IP provider, and T&VS (Test and Verification Solutions), a leading verification services provider for semiconductor IP, hardware and software, today announced a broad collaboration to accelerate the verification of products based on the Codix-Bk series of RISC-V compliant processor cores. The partnership ensures companies can be confident …

BaySand, Codasip, Codeplay and UltraSoC accelerate IoT development with “silicon-to-intelligence” RISC-V platform

Press Releases

MOUNTAIN VIEW, CA, 29th November 2016 BaySand, Codasip, Codeplay and UltraSoC today announced an integrated IoT development platform based on the RISC-V open processor instruction set architecture (ISA).  The platform offers an open-standards-based solution that allows designers of systems-on-a-chip (SoCs) for IoT applications to get from concept to silicon with a high level of software integration in record time and …

Codasip and UltraSoC deliver advanced RISC-V SoC analysis and debug

Press Releases

San Jose, CA – Nov 22nd – Codasip, the leading RISC-V processor IP provider, and UltraSoC, the leading provider of semiconductor IP for on-chip analytics, performance optimization and hardware-based security and debug, announced a broad collaboration to integrate the Codix-Bk series of RISC-V compliant processor cores seamlessly with the UltraSoC environment. As RISC-V based SoCs enter the mainstream, the need …