Codasip to present at Mentor Forums for Emulation in India

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Hyderabad, India | 10 October, 2017 Bangalore, India | 12 October, 2017 As the verification and validation requirements for modern systems become more and more complex, hardware emulation with its versatility becomes the methodology to go to. At Mentor Forums for Emulation 2017, this shift in emulation usage will be explained and discussed through a number of talks by highly …

Does RISC-V mean Open Source Processors?


“So, RISC-V is an Open ISA, that means a RISC-V processor core is Open Source”. This is a statement that I have often heard this year – however, is it true or false? Before answering this, let’s consider the broader issue of whether open standards automatically mean open source. Open standards are widespread in technology. The communication protocols TCP/IP have …

Microsemi and Codasip’s Presentation at DAC 2017


By: Dan Ganousis, Codasip I had the privilege of being a co-presenter with Vijay Subramaniam, Head of IC Design at Microsemi, at this year’s Design Automation Conference in Austin, TX. Our presentation was regarding the benefits Vijay’s group achieved from optimizing the Codasip Bk-3 RISC-V processor core. If you’d like to view the presentation slides, they can be found here. A …

RISC-V automation with Mentor


At this years DAC we had the opportunity to highlight our collaboration with Mentor on RISC-V verification and reuse. To read more about the collaboration, read the online version of the Verification Horizons magazine.  

A Tale of Two Approaches to High-Performance IoT


Extensible Processors vs Accelerators – and how RISC-V changes the dynamic If you were to ask any good designer today what is the best architecture for an SoC that needs to manage complex DSP or high bandwidth traffic demands – you will almost always find the recommendation of using one or more off-the-shelf processors, complimented by hardware accelerators to offload …

Derisking an application-optimized RISC-V processor core


  Automation and verification enables Codasip to give you freedom to customise your processor IP with minimal risk With any processor core it is essential to verify that it is functionally correct. Most processor IP developers will subject their standard cores to extensive functional test suites which will validate conformance to the ISA and stress the processor core under certain …

When a bug really is a feature


How the RISC-V memory model bug shows the real power of an open ISA. No doubt some of you have read about the problem in the proposed RISC-V memory model that received a lot of publicity last week (, and if you have, it’s also worth looking at the formal response on the RISC-V website ( They talk a lot …

RISC-V’s Impact on Processor IP Licensing Fees


… and why you should never believe the incumbent market leader when their market is being disrupted. One subtle way to detect that a mature market is being disrupted is to closely observe the behavior of the market leader. If they “stay the course” you can be reasonably confident that the game changing technology and/or the challenging startup company they …

Exponential Growth of Embedded Processor Innovation


Driven by open standards, and an ecosystem built on co-operation The amazing thing about exponential growth is that you cannot see it when you are looking at it, you can only see it in hindsight. An unrelated, but very interesting reference to this is comes from a blog on the topic of AI The blog has nothing to do …