Codasip Processors Not Affected by Meltdown and Spectre

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In the light of recent news about grave processor security issues, Meltdown and Spectre, we would like to assure customers and partners that Codasip processors are not subject to these issues. Meltdown and Spectre take advantage of a flaw in so-called speculative execution, a feature that allows for faster execution of code. Meltdown exploits the fact that low-privilege code and high-privilege memory are not separated properly …

Codasip to Present at Events in Japan and California

Blog, News & Docs

Busy October brings many events all over the globe where Codasip will be represented. Apart from Mentor Forums for Emulation in India, Codasip’s VPs and directors will be presenting at the following events. Design Solution Forum Yokohama, Japan | 13 October, 2017 On Friday October 13th, Design Solution Forum will take place in Yokohama, Japan. Codasip’s Director for EMEA Business …

Codasip to present at Mentor Forums for Emulation in India

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Hyderabad, India | 10 October, 2017 Bangalore, India | 12 October, 2017 As the verification and validation requirements for modern systems become more and more complex, hardware emulation with its versatility becomes the methodology to go to. At Mentor Forums for Emulation 2017, this shift in emulation usage will be explained and discussed through a number of talks by highly …

Does RISC-V mean Open Source Processors?

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“So, RISC-V is an Open ISA, that means a RISC-V processor core is Open Source”. This is a statement that I have often heard this year – however, is it true or false? Before answering this, let’s consider the broader issue of whether open standards automatically mean open source. Open standards are widespread in technology. The communication protocols TCP/IP have …

Microsemi and Codasip’s Presentation at DAC 2017

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By: Dan Ganousis, Codasip I had the privilege of being a co-presenter with Vijay Subramaniam, Head of IC Design at Microsemi, at this year’s Design Automation Conference in Austin, TX. Our presentation was regarding the benefits Vijay’s group achieved from optimizing the Codasip Bk-3 RISC-V processor core. If you’d like to view the presentation slides, they can be found here. A …

RISC-V automation with Mentor

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At this years DAC we had the opportunity to highlight our collaboration with Mentor on RISC-V verification and reuse. To read more about the collaboration, read the online version of the Verification Horizons magazine. https://verificationacademy.com/verification-horizons/june-2017-volume-13-issue-2/automation-and-reuse-in-risc-v-verification-flow  

A Tale of Two Approaches to High-Performance IoT

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Extensible Processors vs Accelerators – and how RISC-V changes the dynamic If you were to ask any good designer today what is the best architecture for an SoC that needs to manage complex DSP or high bandwidth traffic demands – you will almost always find the recommendation of using one or more off-the-shelf processors, complimented by hardware accelerators to offload …

Learn about RISC-V and IoT @54thDAC

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Codasip is excited to be a co-presenter at this year’s DAC with Vijay Subramaniam, Head of IC Design at Microsemi Corp. Our presentation is Tuesday, June 20th at 1:30pm in Ballroom F. The session is 24.3, our paper is titled “Implementing RISC-V for IoT Applications”. If you would like to arrange a meeting during DAC please email [email protected]

Derisking an application-optimized RISC-V processor core

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  Automation and verification enables Codasip to give you freedom to customise your processor IP with minimal risk With any processor core it is essential to verify that it is functionally correct. Most processor IP developers will subject their standard cores to extensive functional test suites which will validate conformance to the ISA and stress the processor core under certain …