Derisking an application-optimized RISC-V processor core

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Automation and verification enables Codasip to give you freedom to customise your processor IP with minimal risk

With any processor core it is essential to verify that it is functionally correct. Most processor IP developers will subject their standard cores to extensive functional test suites which will validate conformance to the ISA and stress the processor core under certain conditions. As a result, they do not allow any modification rights to their cores, because every change – even the smallest one – requires a major verification effort or a huge risk that the operation of the core will be broken. Therefore you are left with a one-size, not much fitting approach.

With the RISC-V Open ISA, one of the key benefits you have is that the ISA can be extended allowing a processor core to be fine-tuned to the computational requirements of your particular chip. This can give you a very efficient hardware/software implementation for cryptographic, DSP or other computationally-intensive algorithms, which can help differentiate the final SoC product from its competitors.

Every change you make means that the RTL and SDK has to be specifically modified for your custom RISC-V core. Furthermore, verification must be undertaken to ensure the integrity of your optimized core. Additionally, it is important that the verification effort does not adversely impact your SoC timescales while being robust enough to satisfy the needs of your SoC customer.

At the Verification Futures 2017 (VF2017) Conference in Reading, UK, Marcela Zachariasova addressed precisely this challenge, and how Codasip is able to mitigate the risk and deliver greater freedom to our users;

http://www.testandverification.com/conferences/verification-futures/vf2017-europe/vf2017-risc-v-processor-variants-challenges-strategies-functional-verification/ .

Marcela identifies automatic generation of hardware and software design kits as a key factor in verifying a custom processor core.

Automatically generating an optimized processor core (including simulation models, RTL and SDK) is much more rapid than creating such models, the RTL and a compiler by hand. Furthermore, this automation reduces the likelihood of bugs, not just by avoiding typos but by ensuring that the interconnections are flawless and that bit-width conversions or decoder logic are consistent with the high-level spec. Older designers might seen an analogy with the transition to hand optimising logic in schematics to using RTL synthesis. The latter was faster and had a low probability of error. She shows how Codasip Studio automatically generates the HDK and SDK from a high level CodAL description of the Codix-Bk RISC-V IP cores, and also generates a comprehensive UVM verification environment which can check every modification done to the IP.

She also shows that typically, despite the generated verification environment being fully functional and with all reference model checks enabled, it is possible to increase the verification detail/precision by manually written assertions, coverage or directed tests. Moreover, when you verify a RISC-V core variant, it is possible to apply a nice systematic approach of reusing existing manually written parts of the verification environments and retain the verification detail and productivity effectively.

Thus through this two pronged strategy a custom RISC-V processor can be verified rapidly and efficiently.

For our users, this gives them both the freedom and confidence to extend  the processor to the needs of their unique application, while maintaining full compliance with the RISC-V specification. Don’t limit the success of your design with the one-size doesn’t fit all approach, embrace the power of compliance + customization.

Find out more about RISC-V at the 6th RISC-V Workshop in Shanghai, China on May 8-11 2017.