How the RISC-V memory model bug shows the real power of an open ISA.
No doubt some of you have read about the problem in the proposed RISC-V memory model that received a lot of publicity last week (http://www.princeton.edu/engineering/news/archive/?id=17707), and if you have, it’s also worth looking at the formal response on the RISC-V website (https://riscv.org/2017/04/risc-v-memory-consistency-model/). They talk a lot about the technical details, which is not what I plan on discussing today.
So what does this mean for the growing number of people adopting RISC-V?
Before going into why this is actually a good development, let me clarify that this is something that only relates to multi-core shared-memory implementations of a RISC-V design, and is similar to past problems found with both ARM and Intel. A software work-around is possible, at a performance hit (as was the case with ARM), but I am not aware of any commercial implementations of RISC-V that are affected. Since aspects of the RISC-V specifications are still to be ratified (protected mode, and debug being two examples), the current RISC-V implementations tend to be deeply embedded single-core designs. Either as a processor or application accelerator. Next generation designs would certainly have hit this issue, so a big thank you is in order to Princeton for their work.
This brings me to why this is a feature, not of a processor implementation, but of an open ISA like RISC-V.
In a previous blog we talked about how “a rising tide lifts all boats”. As an open ISA, Princeton was able to do this work and publish their findings without any limitation. The result is that all RISC-V vendors now know about the problem and can rapidly adapt their designs. This is all managed out in the open, and at a pace that would be impossible in the closed world. Would we have found out about this problem in our own multi-core testing? Possibly, but it would have taken longer. As they say “many hands make light work”.
Will this be the last issue identified with RISC-V?
While I hope so, however if history is any lesson there will be more. Just search for errata on ARM and Intel processors. You will find that bugs are far more common than people want to admit. However, the openness of the RISC-V community, as well as having so many specialists across a wide range of expertises using RISC-V as a research platform, means issues will be identified early, and addressed rapidly.
Just as we have seen in the SW world, the move to open standards not only led to more robust systems, but a huge increase in the pace of development. That is what makes RISC-V such an exciting place to be.
So while no one likes to hear about a potential bug – it shows that the RISC-V community is working as intended and is raising quality to the highest level.