Disruption in the Embedded Processor Market

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… and it’s not why you expected.

Dan Ganousis
Codasip, LTD

 

Big change is occurring in the embedded processor market … and surprisingly, it’s not just because of RISC-V. If you didn’t spend 2016 stranded on an abandoned island, you’re likely aware of the phenomenal growth of the RISC-V open-source ISA movement. Much the same way Linux quickly outgrew proprietary operating systems like Solaris and HP-UX, RISC-V in 2016 quickly turned the embedded processor market into a duopoly of ISAs … it is soon to be only ARM and RISC-V ISAs in my opinion.

I don’t however consider RISC-V a disruptor. Rather, RISC-V is an enabler and a natural development of the IP market where an innovation commoditizes a market, displacing expensive proprietary technologies. Investopedia defines commoditize as “refers to a process in which goods or services become relatively indistinguishable from competing offerings over time. Generally speaking, commoditized products within specific categories are so similar to one another that the only distinguishing feature is pricing.”

That’s what RISC-V does – it enables true embedded SW portability. RISC-V also reduces IP pricing by reducing the cost of developing embedded processor IP. Embedded processor IP vendors can utilize the RISC-V ISA for free, avoiding the millions of dollars and many man years required to develop their own proprietary ISA.

Processor IP startups benefit from RISC-V commoditization also in that investors are much more willing to fund a startup where the market is known and validated, as in RISC-V. The amount of funding required by an IP startup to launch a new product is greatly reduced. These savings are passed on to the market and consumers benefit via lower IP licensing fees and faster innovation because of increased funding for IP startups.

Innovation is what is disrupting the embedded processor market, not just RISC-V. SoC designers expect that all semiconductor IP is fixed and unchangeable – it’s to be treated like a black box. This common mentality in the SoC design community is due to the legacy business models of ARM, MIPs, CEVA, Imagination Tech and many other IP vendors. It is take for granted by SoC designers – “that’s the way IP has always been and it’s just the way it works – deal with it”.

Let me explain what is the disruptor in the embedded processor market in just three words:

Full Modification Rights

That’s correct. Innovation now allows embedded processor IP to be optimized by SoC designers, automatically. Tools exist that allow SoC designers to easily modify high-level processor models and then automatically create custom RTL, compilers, debuggers, instruction and cycle accurate models, etc. Boom! The entire HDK and SDK is modified and verified automatically based on modifications of the high-level processor model that was provided by your IP vendor. Suddenly, black box processor IP is a thing of the past. A restriction no longer. That’s what I call disruption.

Tools for designing application specific instruction processors (ASIPs) have been around for many years. LisaTek and Target Compilers (both acquired by Synopsys) fielded ASIP tools that automated the process of building a custom processor using a custom ISA. Codasip was the next entrant into this market, and as the last to enter, their innovation and technology was more advanced. All ASIP tool vendors performed well but the market is very small – and thus growth is limited, so investors in these startups have been few and far between.

Codasip is the disruptor of the embedded processor market by applying their ASIP design tools to be used for RISC-V processor optimization. By implementing the RISC-V ISA, Codasip has all the advantages of a commoditized market – essentially lower costs and therefore pricing. But Codasip has avoided the “me too” problem of not being distinguishable in a commoditized market by not just allowing their RISC-V cores to be modified, but actually encouraging SoC designers to modify the Codasip IP to create customized RISC-V cores. Why? Because it makes a big difference. After all, if every product is unique why are all the embedded processors identical? It just makes sense that an optimized embedded processor will enable an optimized electronic product. Who wouldn’t want that if the capability was available and trustworthy?

Codasip’s Studio tool suite has been used for many years by leading semiconductor vendors. These silicon proven tools thus are mature enough for non-processor designers (SoC designers) to use them to tailor an existing RISC-V core in days … not months or years. Check out how SecureRF used Codasip Studio to modify a Codix-Bk 3-stage RISC-V processor to accelerate a security algorithm in silicon, achieving performance acceleration by optimizing an open-source ISA, not by increasing the clock frequency or moving to a smaller process node. That’s disruption. And I believe full modification rights of IP will become the norm, not the exception, very soon. Because you can.

Here’s what is posted on the SecureRF website – in their words, not mine:

“Moving from a software-only implementation to a software implementation with hardware acceleration we were able to reduce the math required to support our DSA signature verification algorithm from 24 instructions to one custom instruction. The ability to use a custom instruction to perform our calculations yielded a powerful performance enhancement. And it was simple. We completed our work using the Codasip tool in just a few days. The results of our benchmarking can be seen in our presentation co-developed with Codasip, RISC-V as a Basis for ASIP Design: A Quantum-Resistant IoT Security Implementation detailing the development of a RISC-V compliant processor, built with Codasip tools, that includes an IoT security application.”

The RISC-V Workshop presentation in July 2016 by SecureRF can be downloaded here for those interested in seeing a market disruption unfolding in front of their eyes:

http://info.securerf.com/risc-v-iot-security-implementation