Using Codasip® Studio (see a screencast) it is possible to customize synthesizable cores or newly design the most suitable processor or SoC for the target applications, as quickly as possible. Time savings are accomplished by automation of tasks that would otherwise be made manually, e.g. creation of programming and simulation tool-chain or of hardware representation. Solution focuses on the challenges associated with specific design tasks that take place both during and after the development of a programmable solution. We understand the technical challenges of the SoCs generation. Solution is a perfect fit for SoC designs targeting.
For modeling of the processor, architecture description language called CodAL is used. The architecture defined in the CodAL model has following key features and major benefits:
| Features | Benefits |
|---|---|
| High-level architectural exploration | Designers can define and thoroughly optimize their processor architecture and instruction set, to reach the best match for algorithm and hardware resources. Thanks to architectural specialization and parallelism, low-power designs can be targeted. |
| Model validation | Based on the CodAL model, the Codasip® validator is able to find fatal errors in the architecture design before own simulation. The fatal error occurs
|
| Toolchain generation | Toolchain for the processor is generated automatically from the CodAL model. |
| Fast and automatic hardware generation | An optimized register-transfer level (RTL) implementation of the processor is generated automatically. Early and accurate feedback about the processors’s area, timing and energy consumption is obtained. |
Consumer, mobile, networking and storage systems with multi-core processors are rapidly becoming more complex. Configuring and verifying multi-core HW/SW architectures, and ensuring that the system can carry its load and data traffic capacities, are all critical tasks. Codasip® delivers tools that automate these tasks to a great extent.
